Electra provides a
set of tools which enhance the productivity of our clients. Using these
products the customers can reduce the total development cost and the time
to market. We have a very aggresive support team that ensures that our
clients requirements are always meet at the earliest. We also provide consultancy
services based on the products.
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Our product set includes
the following.
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Vericomp:
A Verilog-2000
front-end. The tool can compile all features of Verilog95, Verilog2000 and AMS.
Apart from being a Verilog compiler, it can convert a Verilog2000 design
to its equivalent Verilog95. The Verilog2000 to Verilog95 converter
takes a Verilog2000 design and dumps an eqivalent Verilog95. It converted
output keeps track of the original file name and line number information.
The data structure also keeps track of all the book-keeping
information.
The demo version of the tool analyzes and elaborates a design and then dumps
the output into a single file in readable verilog format.
The tool can also be used as a library and can be easily integrated into
other applications. It has a rich set of APIs which makes integration simple.
At present Vericomp is available in Linux Sun and Windows platforms. Please
send an email at info@electra-da.com
for a free evaluation copy.
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Download datasheet :verilog data sheet
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Hierarchical Data Model : This is a C++ data
model for representing structural design. It has a rich set of C++ methods
to effitiently create/manipulate design hierarchy for any application.
It has a Verilog decompiler for easy debugging. It also have some important
applications like hierarchy flattener.
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Verilog test suite`:
This test suite contains test cases for Verilog 2001, Verilog AMS and
System Verilog 3.0. For every new feature of the languages there are a rich
set of test cases, both positive and negative.
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Every test case contains the LRM reference number for which it was written.
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There is also a cross-reference list to name every test case and the corresponding
LRM reference number.
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Each testcase has a bench file for simulation.
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It has a rich set of synthesizable testcases according to IEEE 1364.1
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All the related test cases are grouped together under the same category.
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Inside a group every test case is stored under a directory.
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Inside the final directory, where a single test case is stored there exists
an optional README file.
This test-suite is currently used by leading EDA and semiconductor vendor.
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Download datasheet : test suite
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